109 lines
3.3 KiB
C
109 lines
3.3 KiB
C
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/*
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* Copyright (c) 2021 Valentin Milea <valentin.milea@gmail.com>
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*
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* SPDX-License-Identifier: MIT
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*/
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#include "i2c_slave.h"
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#include "hardware/irq.h"
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typedef struct i2c_slave_t
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{
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i2c_inst_t *i2c;
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i2c_slave_handler_t handler;
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bool transfer_in_progress;
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} i2c_slave_t;
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static i2c_slave_t i2c_slaves[2];
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static inline void finish_transfer(i2c_slave_t *slave) {
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if (slave->transfer_in_progress) {
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slave->handler(slave->i2c, I2C_SLAVE_FINISH);
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slave->transfer_in_progress = false;
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}
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}
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static void __not_in_flash_func(i2c_slave_irq_handler)(i2c_slave_t *slave) {
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i2c_inst_t *i2c = slave->i2c;
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i2c_hw_t *hw = i2c_get_hw(i2c);
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uint32_t intr_stat = hw->intr_stat;
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if (intr_stat == 0) {
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return;
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}
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if (intr_stat & I2C_IC_INTR_STAT_R_TX_ABRT_BITS) {
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hw->clr_tx_abrt;
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finish_transfer(slave);
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}
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if (intr_stat & I2C_IC_INTR_STAT_R_START_DET_BITS) {
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hw->clr_start_det;
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finish_transfer(slave);
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}
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if (intr_stat & I2C_IC_INTR_STAT_R_STOP_DET_BITS) {
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hw->clr_stop_det;
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finish_transfer(slave);
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}
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if (intr_stat & I2C_IC_INTR_STAT_R_RX_FULL_BITS) {
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slave->transfer_in_progress = true;
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slave->handler(i2c, I2C_SLAVE_RECEIVE);
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}
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if (intr_stat & I2C_IC_INTR_STAT_R_RD_REQ_BITS) {
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hw->clr_rd_req;
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slave->transfer_in_progress = true;
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slave->handler(i2c, I2C_SLAVE_REQUEST);
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}
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}
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static void __not_in_flash_func(i2c0_slave_irq_handler)() {
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i2c_slave_irq_handler(&i2c_slaves[0]);
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}
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static void __not_in_flash_func(i2c1_slave_irq_handler)() {
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i2c_slave_irq_handler(&i2c_slaves[1]);
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}
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void i2c_slave_init(i2c_inst_t *i2c, uint8_t address, i2c_slave_handler_t handler) {
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assert(i2c == i2c0 || i2c == i2c1);
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assert(handler != NULL);
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uint i2c_index = i2c_hw_index(i2c);
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i2c_slave_t *slave = &i2c_slaves[i2c_index];
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slave->i2c = i2c;
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slave->handler = handler;
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// Note: The I2C slave does clock stretching implicitly after a RD_REQ, while the Tx FIFO is empty.
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// There is also an option to enable clock stretching while the Rx FIFO is full, but we leave it
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// disabled since the Rx FIFO should never fill up (unless slave->handler() is way too slow).
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i2c_set_slave_mode(i2c, true, address);
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i2c_hw_t *hw = i2c_get_hw(i2c);
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// unmask necessary interrupts
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hw->intr_mask = I2C_IC_INTR_MASK_M_RX_FULL_BITS | I2C_IC_INTR_MASK_M_RD_REQ_BITS | I2C_IC_RAW_INTR_STAT_TX_ABRT_BITS | I2C_IC_INTR_MASK_M_STOP_DET_BITS | I2C_IC_INTR_MASK_M_START_DET_BITS;
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// enable interrupt for current core
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uint num = I2C0_IRQ + i2c_index;
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irq_set_exclusive_handler(num, i2c_index == 0 ? i2c0_slave_irq_handler : i2c1_slave_irq_handler);
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irq_set_enabled(num, true);
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}
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void i2c_slave_deinit(i2c_inst_t *i2c) {
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assert(i2c == i2c0 || i2c == i2c1);
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uint i2c_index = i2c_hw_index(i2c);
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i2c_slave_t *slave = &i2c_slaves[i2c_index];
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assert(slave->i2c == i2c); // should be called after i2c_slave_init()
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slave->i2c = NULL;
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slave->handler = NULL;
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slave->transfer_in_progress = false;
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uint num = I2C0_IRQ + i2c_index;
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irq_set_enabled(num, false);
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irq_remove_handler(num, i2c_index == 0 ? i2c0_slave_irq_handler : i2c1_slave_irq_handler);
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i2c_hw_t *hw = i2c_get_hw(i2c);
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hw->intr_mask = I2C_IC_INTR_MASK_RESET;
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i2c_set_slave_mode(i2c, false, 0);
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}
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